Initially the loader can be booted up without setting the RAM. This is achieved by the stepping stone controller. This controller fetches first 4KB of data from the NAND flash and places it in the 4KB SRAM called the stepping stone buffer.
This SRAM is good enough for the loader to load the MDK OS. To do anything serious we need to setup the SDRAM.
To proceed further we need to understand the datasheet thoroughly.
From the datasheet we have:
Our memory being the K4S561632N its organization is 4 x 4,194,304 words by 16bits (i.e. 16M x 16). The x16 forms the data bus width i.e. 16 bits or 2 bytes. The "words" in the above sentence means this data bus width i.e. 16 bits. Hence the SDRAM outputs a "word".
Also here 268,435,456 bits is 32MB or 256Mb.
Notice that all the memories have "4 x " prefix. This is because all these memories have 4 banks and therefore are 4 bank operation chips.
The organization in the data sheet is as follows for the 3 different memories:
In this case our memory organization is the 16Mx16 with Row Address from A0~A12 and Column Address from A0-A8.
Hence we can have 2^13 addressable rows and 2^9 addressable columns to make it 4194304 addressable words in each bank. Hence 4 banks x 4194304 addressable words become a total of 16777216 words. Since each word is 16 bits or 2 bytes the chip capacity is 32MB (=16777216 x 2 bytes (16 bits) = 33554432 or 32MB).
Similarly we can figure out the numbers for the other 2 memories.
For the K4S560832N:
4 x 8,388,608 words = 33554432 words.
Since it is 8 bits per word or 1 byte per word it is 33554432 x 1 = 33554432 or 32MB.
For the K4S560432N:
4 x 16,777,216 = 67108864 words.
Since it is 4 bits per word or 1/2 a byte per word it is 67108864 x 1/2 = 33554432 or 32MB.
Now we come to how these memory chips are wired to our processor. A diagram of how the chips are wired to the processor is below (ASCII art courtesy of Juergen Borleis of Pengutronix mailing list for helping me understand the bank map configuration):
If we go back to schematic we can find that nGCS6 with net name LLnSCS0 is connected to nSCS (SDRAM Chip Select) input of the two 32 MB chips.
According to the data sheet the nGCS6 forms Bank 6. Hence the two SDRAM chips are connected to Bank6 with both 16 bit bus width forming connected to the 32 bit data bus of the processor. You can verify this in the schematic snapshot below:
You can see that the LDATA0 to LDATA15 connections from chip1 and LDATA16 to LDATA31 from chip2 forming the 32 bit data bus width.
When an address say 'A' is sent on the address lines for a read from the address then the chip U6 will respond with the data set in address 'A' through LDATA0 - LDATA15. Since the same address lines are fed to chip U7 it too responds with the data set in address 'A' through LDATA16 - LDATA31. When a write is done to address 'A', the first 16 bit data is set in the address 'A' of chip U6 and the send 16 bit data is set in address 'A' of chip U7.
Notice that the address pin connections start at ADDR2. For a 32 bit data bus the address is at 4 byte boundaries.
Notice that LADDR24 and LADDR25 lines are set as inputs to BA0 and BA1 respectively. BA0 and BA1 forms bank select pins for the chip.
Now why is LADDR24 and LADDR25 pins selected?
Here the DW6 parameter is set to DW6_32b i.e. bus width as 32 bit.
My SDRAM init is as follows:
I set the BANKCON6 register to Sync DRAM as it is SDRAM (Synchronous DRAM). For the memory type of SDRAM I set SCAN parameter to SCAN_9BIT as it is A0-A8 or 9 bit.
Bank7 has to be disabled. Set the BANKCON7 register to MT_ROM_SRAM as it is set default to MT_SYNC_DRAM which should be removed.
There is Trcd or RAS to CAS delay to set. In the datasheet the RAS to CAS latency or Trcd(min) is 20ns. In our processor we have setup the HCLK to be 101 Mhz or 9.99ns ~ 10ns. Hence we have to setup or Trcd to have to 2 clock delay which is 00.
Refresh control register (REFRESH):
We set REFEN which is self auto refresh.
We set TREFMD to 0 CBR/Auto refresh mode.
We set the SDRAM RAS pre-charge time to 2 clocks i.e. value 00 as the data sheet gives a tRP(min) as 20ns or 2 clock cycles.
We set the SDRAM semi row cycle time Tsrc to Tsrc_5. The calculation is as follows:
Trc = Tsrc + Trp
or
Tsrc = Trc - Trp
From the data sheet we have Trc as 65ns Trp as 20 ns. Hence we get Tsrc as 45ns. Hence we set Tsrc_5 which is 5 clocks or 50ns.
I set the refresh counter to 1269 as given in the data sheet example.
Banksize register settings (BANKSIZE):
Here I enable BURST_EN(burst enable), SCKE_EN (SDRAM power down mode enable), SCLK_EN (SCLK being enabled during SDRAM access cycle to reduce power consumption) and BANK76MAP set to 001 or 64MB as the size of the memory is 32MiB + 32MiB = 64MiB.
SDRAM Mode register set register (MRSR):
We simply set the CL parameter or the CAS Latency to 2 clocks. According to the data sheet the CAS latency is 2.
A note on the memory controller bank select:
The S3C2440 has 8 memory banks. The General Chip select or nGCS should be connected to the different chip selects of the various peripherals connected which use the address space.
The banks are activated when the address of a memory is within the address region of the bank. This takes the burden out of doing a chip select manually whenever you want to access the memory region. Hence you can multiplex the address lines to different chips in different banks. When an address is generated the chip in the memory region is automatically selected using the bank chip select signal. I will verify this and provide an oscilloscope trace.
For reference from the data sheet:
Conclusion:
We do all the SDRAM setup in the loader itself as the MDK OS is loaded onto the SDRAM.
References: http://thread.gmane.org/gmane.comp.embedded.ptxdist.oselas.community/1994/focus=2010
Schematics from FriendlyARM.
Data sheet snapshots from Samsung S3C2440 data sheet.
Memory organization snap shots from Samsung K4S561632N data sheet.
This SRAM is good enough for the loader to load the MDK OS. To do anything serious we need to setup the SDRAM.
My setup:
In my MINI2440 board I have two Samsung K4S561632N SDRAM chips each of size 32MB totalling 64MB of SDRAM.To proceed further we need to understand the datasheet thoroughly.
From the datasheet we have:
The K4S560432N / K4S560832N / K4S561632N is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits.The SRAM type table is as follows:
Our memory being the K4S561632N its organization is 4 x 4,194,304 words by 16bits (i.e. 16M x 16). The x16 forms the data bus width i.e. 16 bits or 2 bytes. The "words" in the above sentence means this data bus width i.e. 16 bits. Hence the SDRAM outputs a "word".
Also here 268,435,456 bits is 32MB or 256Mb.
Notice that all the memories have "4 x " prefix. This is because all these memories have 4 banks and therefore are 4 bank operation chips.
The organization in the data sheet is as follows for the 3 different memories:
In this case our memory organization is the 16Mx16 with Row Address from A0~A12 and Column Address from A0-A8.
Hence we can have 2^13 addressable rows and 2^9 addressable columns to make it 4194304 addressable words in each bank. Hence 4 banks x 4194304 addressable words become a total of 16777216 words. Since each word is 16 bits or 2 bytes the chip capacity is 32MB (=16777216 x 2 bytes (16 bits) = 33554432 or 32MB).
Similarly we can figure out the numbers for the other 2 memories.
For the K4S560832N:
4 x 8,388,608 words = 33554432 words.
Since it is 8 bits per word or 1 byte per word it is 33554432 x 1 = 33554432 or 32MB.
For the K4S560432N:
4 x 16,777,216 = 67108864 words.
Since it is 4 bits per word or 1/2 a byte per word it is 67108864 x 1/2 = 33554432 or 32MB.
Now we come to how these memory chips are wired to our processor. A diagram of how the chips are wired to the processor is below (ASCII art courtesy of Juergen Borleis of Pengutronix mailing list for helping me understand the bank map configuration):
----------+ /CS to bank#2
|----------------------------------------------------------
| | |
S3C2440 | /CS to bank#1 | |
|------------------------------ | |
| | | | |
| +--------+ +--------+ +--------+ +--------+
| | SDRAM1 | | SDRAM2 | | SDRAM3 | | SDRAM4 |
| | | | | | | | |
| +--------+ +--------+ +--------+ +--------+
| 0..15 | |16..31 0..15| |16..31
| | | | |
|----------------------------------------------------------
| 32 bit databus
|
----------+
If we go back to schematic we can find that nGCS6 with net name LLnSCS0 is connected to nSCS (SDRAM Chip Select) input of the two 32 MB chips.
Coming back to the data sheet we see that nGCS6 starts at memory address 0x30000000. Hence our SDRAM memory address starts from 0x30000000. The snapshot of the memory map is below:
According to the data sheet the nGCS6 forms Bank 6. Hence the two SDRAM chips are connected to Bank6 with both 16 bit bus width forming connected to the 32 bit data bus of the processor. You can verify this in the schematic snapshot below:
You can see that the LDATA0 to LDATA15 connections from chip1 and LDATA16 to LDATA31 from chip2 forming the 32 bit data bus width.
When an address say 'A' is sent on the address lines for a read from the address then the chip U6 will respond with the data set in address 'A' through LDATA0 - LDATA15. Since the same address lines are fed to chip U7 it too responds with the data set in address 'A' through LDATA16 - LDATA31. When a write is done to address 'A', the first 16 bit data is set in the address 'A' of chip U6 and the send 16 bit data is set in address 'A' of chip U7.
Notice that the address pin connections start at ADDR2. For a 32 bit data bus the address is at 4 byte boundaries.
Notice that LADDR24 and LADDR25 lines are set as inputs to BA0 and BA1 respectively. BA0 and BA1 forms bank select pins for the chip.
Now why is LADDR24 and LADDR25 pins selected?
- There are 4 banks per chip. Hence the 2 bit combination will allow to select the 4 banks.
- If the bits below LADDR24 are set to 1 it becomes 0xFFFFFF which is 16777215(starting from 0) which is the size of the 4 banks. (4 x4M words). Since the address starts at LADDR2 shift the LADDR24 and LADDR25 by 2 bits to the right. Now we get 0x3FFFFF which is 4194303 (starting from 0) which is the size of the single bank. A 4194304 address switches the bank to 1. Hence as far as I see this is the explanation for the bank switching using the addresses themselves i.e. when the bits of the addresses corresponding to banks change there is a bank switch.
Register setup:
We finally come to source code for the SDRAM setup.
First we need to configure Bus Width and Wait Control register (BWSCON)
The code is as follows:
1 2 3 4 5 6 7 8 | void config_bwscon() { /* Configure BWSCON */ writereg32(BWSCON_REG(MEM_BA), DW7_RESERVED|DW6_32b|DW5_RESERVED|DW4_RESERVED| DW3_RESERVED|DW2_RESERVED|DW1_RESERVED); } |
Here the DW6 parameter is set to DW6_32b i.e. bus width as 32 bit.
My SDRAM init is as follows:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | void sdram_init() { config_bwscon(); /* Configure BANKCON6/BANKCON7 */ writereg32(BANKCON6_REG(MEM_BA),MT_SYNC_DRAM|SCAN_9BIT); /* * Set BANKCON7 to ROM/SRAM i.e 00 and not SYNC_DRAM. * Rest of the values should not be used as they are reserved * Default value is SYNC_DRAM which should not be used. */ writereg32(BANKCON7_REG(MEM_BA),MT_ROM_SRAM); /* Configure SDRAM Refresh settings */ writereg32(REFRESHCTL_REG(MEM_BA),REFEN|Tsrc_5|1269); /* Configure Banksize setting */ writereg32(BANKSIZE_REG(MEM_BA),BURST_EN|SCKE_EN|SCLK_EN|BK76MAP_64MB); /* Configure mode set register for BANK6 */ writereg32(MRSRB6_REG(MEM_BA),CAS_LATENCY_2CLK); return; } |
I set the BANKCON6 register to Sync DRAM as it is SDRAM (Synchronous DRAM). For the memory type of SDRAM I set SCAN parameter to SCAN_9BIT as it is A0-A8 or 9 bit.
Bank7 has to be disabled. Set the BANKCON7 register to MT_ROM_SRAM as it is set default to MT_SYNC_DRAM which should be removed.
There is Trcd or RAS to CAS delay to set. In the datasheet the RAS to CAS latency or Trcd(min) is 20ns. In our processor we have setup the HCLK to be 101 Mhz or 9.99ns ~ 10ns. Hence we have to setup or Trcd to have to 2 clock delay which is 00.
Refresh control register (REFRESH):
We set REFEN which is self auto refresh.
We set TREFMD to 0 CBR/Auto refresh mode.
We set the SDRAM RAS pre-charge time to 2 clocks i.e. value 00 as the data sheet gives a tRP(min) as 20ns or 2 clock cycles.
We set the SDRAM semi row cycle time Tsrc to Tsrc_5. The calculation is as follows:
Trc = Tsrc + Trp
or
Tsrc = Trc - Trp
From the data sheet we have Trc as 65ns Trp as 20 ns. Hence we get Tsrc as 45ns. Hence we set Tsrc_5 which is 5 clocks or 50ns.
I set the refresh counter to 1269 as given in the data sheet example.
Banksize register settings (BANKSIZE):
Here I enable BURST_EN(burst enable), SCKE_EN (SDRAM power down mode enable), SCLK_EN (SCLK being enabled during SDRAM access cycle to reduce power consumption) and BANK76MAP set to 001 or 64MB as the size of the memory is 32MiB + 32MiB = 64MiB.
SDRAM Mode register set register (MRSR):
We simply set the CL parameter or the CAS Latency to 2 clocks. According to the data sheet the CAS latency is 2.
A note on the memory controller bank select:
The S3C2440 has 8 memory banks. The General Chip select or nGCS should be connected to the different chip selects of the various peripherals connected which use the address space.
The banks are activated when the address of a memory is within the address region of the bank. This takes the burden out of doing a chip select manually whenever you want to access the memory region. Hence you can multiplex the address lines to different chips in different banks. When an address is generated the chip in the memory region is automatically selected using the bank chip select signal. I will verify this and provide an oscilloscope trace.
For reference from the data sheet:
Conclusion:
We do all the SDRAM setup in the loader itself as the MDK OS is loaded onto the SDRAM.
References: http://thread.gmane.org/gmane.comp.embedded.ptxdist.oselas.community/1994/focus=2010
Schematics from FriendlyARM.
Data sheet snapshots from Samsung S3C2440 data sheet.
Memory organization snap shots from Samsung K4S561632N data sheet.
It is better to do the right problem the wrong way than the wrong problem the right way. --Richard Hamming
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