Clocks form an important part in any embedded system and configuration of this clock tree is very error prone. In the present code clean up I have parametrized the existing configurations which were hard coded. This is very error prone as any change in the base clock speed would cause a mismatch with the configuration.
The first step I took in refactoring my code was to have helper functions to get FCLK, HCLK and PCLK. In the same vein I created a conditional compilation set up which compiles based on the board i.e. it being a MINI2440 or a MINI2410 etc. From the clock point of view the crystal used in these boards varies. The MINI2440 uses a clock source derived from a crystal based on OM3 and OM2 pins. The crystal as per the schematic is a 12Mhz crystal.
With this as the base and using the helper functions the whole clock tree settings i.e the pre-scaler can be automated for different peripherals such as UART, SD MMC using formulae rather than hard coding values.
First we will try to understand the different clocks signals generated by the control logic. There are 3 clock signals generated FCLK for the CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.
The S3C2440 has 2 PLL's one for FCLK, HCLK and PCLK and the other dedicated for USB block (48 MHz). The control logic can make slow clocks without the PLL's.
What is a PLL and what does it do? PLL or a Phase Locked Loop is a control system which generates an output signal whose phase is related to the phase of the input signal. Generally we use a PLL to generate a multiple of the input frequency. So the input to the PLL is a oscillator and output is a multiple of the input frequency. So in our case we have a 12MHz crystal oscillator which is given to the PLL's to generate multiples and keeping the phase locked with the input and output frequencies.
PLL's take time to stabilize. Hence there should be a way for the chip to work based on the oscillator frequency or an external signal. Once the PLL stabilizes and is able to generate a clean signal the chip can switch to the PLL frequency.
The following is the clock architecture of the S3C2440.
The main clock comes from the external crystal (XTlpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLL's (Phase locked loop) which generate the high frequency clock required in the S3C2440A.
The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET as shown below
According to the data sheet the clock selection during boot-up is Crystal for the main clock source and USB.
The MPLL starts just after a reset but the MPLL output is not used as the system clock until the software writes valid settings to the MPLLCON register. Before these settings, the clock from the external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of the MPLLCON register, the user should write the same value into the MPLLCON register.
After the power on reset the crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the OSC (XTIpll) clock the PLL starts to operate according the default PLL configuration. However the PLL is commonly known to be unstable after power-on reset so Fin is fed directly to the FCLK instead of the Mpll (PLL output) before the software newly configures PLLCON.
The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.
The wave form diagram below gives a clearer picture
For USB clock control and USB device interface needs 48MHz clock hence a dedicated USB PLL (UPLL) generates the clock.
Now we come to coding the clock setup. The clock setup has to be parameterized.
We come to the init_clock(..) function. Here we set the clock lock time to maximum. Next we do a set_clock_divn(..). Here we set the dividers. We divide the FCLK by 1, HDIVN by 4 and PDIVN by 8. Note that MPLL is fed into the CLKCNTL logic which generates the FCLK.
So the final clock setup would be:
FCLK = 405 MHz.
HCLK = 405/4 = 101MHz
PCLK = 405/8 = 50 MHz
We need to setup the CPU to asynchronous mode. We can see the P 2-11 of ARM920T (Chapter 5). Also S3C2440 does not support synchronous mode.
The code is as follows:
Next we have to set the 2 PLL's. MPLL and UPLL.
First we set the UPLL to generate 48 MHz as follows:
Note the mov r0,r0. This is used generate at least 7 NOPs.
Next we set the MPLL to 405 MHz as follows:
Finally we clear the slow clock register bits as follows.
We clear the UCLK bit to turn on UPL. Next we turn on the MPLL and allow it settle which takes 300us. Hence we have NOPs for the delay. After this we turn OFF the slow clock to set the MPLL to the FCLK.
To get the current clocks I have written utility functions so that I can derive the different clocks just by reading the registers itself.
First I have helper functions to get the dividers as follows:
Next I get the 2 PLL clock i.e. UPLL and MPLL based on the following helper functions:
To explain the above code I have to bring out the formulae. According the datasheet:
MPLL Control Register
Mpll = (2 * m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV
UPLL Control Register
Upll = (m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV
Hence we get the m, p and s.
Next we have the formula:
PLL Value Selection Guide (MPLLCON)
So to finally get the FCLK, HCLK,PCLK and the UCLK we have to check the dividers. We do divide the FCLK so we use Fout as is. Next for HCLK,PCLK and UCLK we have the following code:
Note that the FCLK forms the base for the HCLK i.e. we divide the FCLK to get the HCLK. Next for the PCLK, HCLK forms the base i.e. we divide the HCLK to get the PCLK.
For the UCLK we have the UPLL and hence we check the UDIVN and divide to get the final clock.
So there you have it. The clock setup for the S3C2440.
The first step I took in refactoring my code was to have helper functions to get FCLK, HCLK and PCLK. In the same vein I created a conditional compilation set up which compiles based on the board i.e. it being a MINI2440 or a MINI2410 etc. From the clock point of view the crystal used in these boards varies. The MINI2440 uses a clock source derived from a crystal based on OM3 and OM2 pins. The crystal as per the schematic is a 12Mhz crystal.
With this as the base and using the helper functions the whole clock tree settings i.e the pre-scaler can be automated for different peripherals such as UART, SD MMC using formulae rather than hard coding values.
First we will try to understand the different clocks signals generated by the control logic. There are 3 clock signals generated FCLK for the CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.
The S3C2440 has 2 PLL's one for FCLK, HCLK and PCLK and the other dedicated for USB block (48 MHz). The control logic can make slow clocks without the PLL's.
What is a PLL and what does it do? PLL or a Phase Locked Loop is a control system which generates an output signal whose phase is related to the phase of the input signal. Generally we use a PLL to generate a multiple of the input frequency. So the input to the PLL is a oscillator and output is a multiple of the input frequency. So in our case we have a 12MHz crystal oscillator which is given to the PLL's to generate multiples and keeping the phase locked with the input and output frequencies.
PLL's take time to stabilize. Hence there should be a way for the chip to work based on the oscillator frequency or an external signal. Once the PLL stabilizes and is able to generate a clean signal the chip can switch to the PLL frequency.
The following is the clock architecture of the S3C2440.
The main clock comes from the external crystal (XTlpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLL's (Phase locked loop) which generate the high frequency clock required in the S3C2440A.
The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET as shown below
The MPLL starts just after a reset but the MPLL output is not used as the system clock until the software writes valid settings to the MPLLCON register. Before these settings, the clock from the external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of the MPLLCON register, the user should write the same value into the MPLLCON register.
After the power on reset the crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the OSC (XTIpll) clock the PLL starts to operate according the default PLL configuration. However the PLL is commonly known to be unstable after power-on reset so Fin is fed directly to the FCLK instead of the Mpll (PLL output) before the software newly configures PLLCON.
The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.
The wave form diagram below gives a clearer picture
For USB clock control and USB device interface needs 48MHz clock hence a dedicated USB PLL (UPLL) generates the clock.
Now we come to coding the clock setup. The clock setup has to be parameterized.
We come to the init_clock(..) function. Here we set the clock lock time to maximum. Next we do a set_clock_divn(..). Here we set the dividers. We divide the FCLK by 1, HDIVN by 4 and PDIVN by 8. Note that MPLL is fed into the CLKCNTL logic which generates the FCLK.
1 2 3 4 | set_clock_divn(CLK_BASE_ADDR,
DIVN_UPLL_BY_1,
HDIVN_FCLK_BY_4,
PDIVN_HCLK_BY_2);
|
So the final clock setup would be:
FCLK = 405 MHz.
HCLK = 405/4 = 101MHz
PCLK = 405/8 = 50 MHz
We need to setup the CPU to asynchronous mode. We can see the P 2-11 of ARM920T (Chapter 5). Also S3C2440 does not support synchronous mode.
The code is as follows:
1 2 3 4 5 6 7 8 | __asm__ __volatile__( "mrc p15,0,r1,c1,c0,0\n\t" "orr r1,r1,#0xC0000000\n\t" "mcr p15,0,r1,c1,c0,0\n\t" : /* No output */ : /* No input */ : "r1" /* r1 clobbered */ ); |
Next we have to set the 2 PLL's. MPLL and UPLL.
First we set the UPLL to generate 48 MHz as follows:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 | set_clk_upll(CLK_BASE_ADDR,0x38,0x2,0x2); //48 MHz. __asm__ __volatile__( "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" ); |
Note the mov r0,r0. This is used generate at least 7 NOPs.
Next we set the MPLL to 405 MHz as follows:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 | set_clk_mpll(CLK_BASE_ADDR,0x7f,0x2,0x1); //405 MHz __asm__ __volatile__( "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" "mov r0,r0\n\t" ); |
Finally we clear the slow clock register bits as follows.
1 2 3 4 5 6 7 8 9 10 11 12 13 | #define clear_slow_clock(BA) do { \ clear_reg_bits(CLKSLOW_REG(BA),UCLK_ON); \ clear_reg_bits(CLKSLOW_REG(BA),MPLL_OFF); \ __asm__ __volatile__ ( \ "mov r0,r0 \n\t" \ "mov r0,r0 \n\t" \ "mov r0,r0 \n\t" \ "mov r0,r0 \n\t" \ "mov r0,r0 \n\t" \ "mov r0,r0 \n\t" \ ); \ clear_reg_bits(CLKSLOW_REG(BA),SLOW_BIT); \ } while(0) |
We clear the UCLK bit to turn on UPL. Next we turn on the MPLL and allow it settle which takes 300us. Hence we have NOPs for the delay. After this we turn OFF the slow clock to set the MPLL to the FCLK.
To get the current clocks I have written utility functions so that I can derive the different clocks just by reading the registers itself.
First I have helper functions to get the dividers as follows:
1 2 3 4 5 6 7 8 | #define get_clk_pll_mdiv(PLL_REG) \ (((readreg32(PLL_REG)) & MDIV_MASK) >> MDIV_SHIFT) #define get_clk_pll_pdiv(PLL_REG) \ (((readreg32(PLL_REG)) & PDIV_MASK) >> PDIV_SHIFT) #define get_clk_pll_sdiv(PLL_REG) \ (((readreg32(PLL_REG)) & SDIV_MASK) >> SDIV_SHIFT) |
Next I get the 2 PLL clock i.e. UPLL and MPLL based on the following helper functions:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | uint32_t get_mpll_clk(uint32_t BA) { uint32_t m,p,s; m = get_clk_pll_mdiv(MPLLCON_REG(BA)) + 8; p = get_clk_pll_pdiv(MPLLCON_REG(BA)) + 2; s = get_clk_pll_sdiv(MPLLCON_REG(BA)); return ((m * S3C_CLOCK_REFERENCE) * 2)/(p * (1<<s)); } uint32_t get_upll_clk(uint32_t BA) { uint32_t m,p,s; m = get_clk_pll_mdiv(UPLLCON_REG(BA)) + 8; p = get_clk_pll_pdiv(UPLLCON_REG(BA)) + 2; s = get_clk_pll_sdiv(UPLLCON_REG(BA)); return (m * S3C_CLOCK_REFERENCE)/(p * (1<<s)); } |
To explain the above code I have to bring out the formulae. According the datasheet:
MPLL Control Register
Mpll = (2 * m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV
UPLL Control Register
Upll = (m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV
Hence we get the m, p and s.
Next we have the formula:
PLL Value Selection Guide (MPLLCON)
- Fout = 2 * m * Fin / (p*(2^s) ), Fvco = 2 * m * Fin / p where: m=MDIV+8, p=PDIV+2, s=SDIV
- 600MHz ≤ FVCO ≤ 1.2GHz
- 200MHz ≤ FCLK OUT ≤ 600MHz
So to finally get the FCLK, HCLK,PCLK and the UCLK we have to check the dividers. We do divide the FCLK so we use Fout as is. Next for HCLK,PCLK and UCLK we have the following code:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 | uint32_t get_hclk(uint32_t BA) { uint32_t fclk = get_fclk(BA); switch(get_clock_hdivn(BA)) { case HDIVN_FCLK_BY_1: return fclk; case HDIVN_FCLK_BY_2: return (fclk >> 1); case HDIVN_FCLK_BY_4: //TODO: CAMDIVN conditon check pending. return (fclk >> 2); case HDIVN_FCLK_BY_3: //TODO: CAMDIVN conditon check pending. return (fclk / 3); } return fclk; } uint32_t get_pclk(uint32_t BA) { uint32_t hclk = get_hclk(BA); switch(get_clock_pdivn(BA)) { case PDIVN_HCLK_BY_1: return hclk; case PDIVN_HCLK_BY_2: return hclk >> 1; } return hclk; } uint32_t get_uclk(uint32_t BA) { uint32_t uclk = get_upll_clk(BA); switch(get_clock_upll_divn(BA)) { case DIVN_UPLL_BY_1: return uclk; case DIVN_UPLL_BY_2: return uclk >> 2; } return uclk; } |
Note that the FCLK forms the base for the HCLK i.e. we divide the FCLK to get the HCLK. Next for the PCLK, HCLK forms the base i.e. we divide the HCLK to get the PCLK.
For the UCLK we have the UPLL and hence we check the UDIVN and divide to get the final clock.
So there you have it. The clock setup for the S3C2440.
Time is an illusion
--Albert Einstein
