Monday 29 August 2016

Pidgin setup for Microsoft Communicator/Lync/Skype

Let me break the hiatus by writing a small post on the setup of pidgin for MS Communicator/Skype. This applies to my network and might vary in your case. Internet resources for setup does not somewhat give a complete picture. Hence I decided to do a writeup.

The base data is that the network uses Skype for Business and Office 365. Hence we need to do the following:

  1. Download pidgin using apt.
  2. Download pidgin-sipe package using apt.
Next start up pidgin and do the following settings:

  1. In the Accounts window (Accounts -> Manage Accounts)  select Add.
  2. Go to "Basic" tab
  3. Select "Office Communicator" as the protocol.
  4. For user name enter it in the format of the email address of your office 365 account.
  5. For "Login" field I enter in the format of "DOMAIN\user". Here "user" being the ldap login user name for your office 365 account.
  6. Enter your password in the password field and check the box "Remember password"
  7. Go to "Advanced" tab.
  8. Enter "Auto" in connection type.
  9. I have entered the User agent string as : "UCCAPI/16.0.6001.1073 OC/16.0.6001.1073 (Skype for Business)" minus the quotes. If you get an error please try other User agent strings as recommended in the FAQ given here: https://sourceforge.net/p/sipe/wiki/Frequently%20Asked%20Questions/#connection-refused-with-error-messagewzxhzdk12you-are-currently-not-using-the-recommended-version-of-the-clientwzxhzdk13you-have-been-rejected-by-the-server-httpsportalmicrosoftonlinecomdownloadlyncaspx
  10. Select the Authentication Scheme as "NTLM". It might vary for your network. Please try different options if the one I selected does not work.
  11. Keep all other options as defaults.
  12. In the proxy tab select "Environment Settings".
  13. Enable the account in the Accounts tab.
  14. Restart pidgin if needed. 
 Enjoy communication with your colleagues.

If people do not believe that mathematics is simple, it is only because they do not realize how complicated life is.
-John Von Neumann

Saturday 6 August 2016

Slow updates

In the past few months life has taken a tough turn. It keeps getting harder and harder to concentrate on anything when mental peace is elusive. I have decided to slow things down a little bit and take things slowly. Hopefully I will be able to get back fresh and continue with my passion and thereby educate you, the viewers with my blog posts. You can always mail or comment on my posts which will help me get me strength.

So wish me luck!

Saturday 9 July 2016

Linux dts compilation using dtc compiler.

I was reading up on the dts (Device Tree Specification) specification and wanted to try out custom dts and compile it to dtb (Device Tree Blob).

The dts I wanted to compile was for the Wandboard which is the imx6dl-wandboard.dts

To compile I use the following command:

dtc -I dts -O dtb -o imx6dl-wandboard_test.dts

When trying this I get the error "FATAL ERROR: Unable to parse input tree near the includes..."

Turns out we have to use CPP (C Preprocessor)  to parse the includes and substitutions. Hence the next command is as follows:

cpp -nostdinc -I include -undef, -x assembler-with-cpp imx6dl-wandboard.dts > imx6dl-wandboard_bare.dts

 Here we use

-nostdinc:  We do not search system directories for header files. Only the directories I have specified wtih the -I are searched for header files.

-undef: We do not perform any system-specific or GCC-specific macros. All standard predefined macros remain definied.

-x: We provide the option assembler-with-cpp as the dtc compiler cannot auto ditacte whether the file is a "open", "clode", "read and write"

Pass the dts file and redirect the output to an output dts file.
Next we run the dtc compiler as above replacing imx6dl-wandboard_test.dts with the output generated from CPP. This will create the dtb file . You reverse the dtb to a dts by replacing the -I parameter with dtb and -O parameter with dts.

Also make sure you run this command in the arch/arm/boot/dts directory because of the includes present in it. Replace the "arm" with your CPU architecture of choice.

Additionally you can also create the dtb file running the rule dtbs in the makefile.

To make it work edit the Makefile in the arch/arm/boot/dts and add your dts file in the proper architecture. For my wandboard it will be dtb-$(CONFIG_ARCH_MXC).

Next create the dtb file with the following command:

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ARCH=arm CROSS_COMPILE=`pwd`/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androideabi- make -C kernel_imx/ dtbs



References: https://linux-sunxi.org/Device_Tree#Compiling_the_Device_Tree

"There must be no barriers to freedom of inquiry … There is no place for dogma in science. The scientist is free, and must be free to ask any question, to doubt any assertion, to seek for any evidence, to correct any errors."
--J Robert Oppenheimer



Friday 8 July 2016

Running bootchart in Android Marshmallow

For the Wandboard that I was customizing I wanted to know the process statistics, processor usage and IO usage to speed up my boot up time. I decided it was time to run bootchart.

There is quite a bit of outdated Internet resources on how to use bootchart for Android. I decided to write one:

First enable bootchart by doing a adb shell "echo 120 > /data/bootchart/start". This would tell the init to start bootcharting for 2 minutes. After this you get a set of files in the /data/bootchart directory. The files are generally as follows:

header
kernel_pacct
proc_diskstats.log
proc_ps.log
proc_stat.log



Next run the shell program grab-bootchart.sh in system/core/init which will use the measurement files above into a visual file either .png, .swf which shows the different processes hogging the CPU and which processes take a long time to init. Before we conclude a boot chart below of my wandboard custom build (Click for a larger image or download it to zoom in).





Anyone who considers arithmetical methods of producing random digits is, of course, in a state of sin.
 -Jon Von Neumann

Saturday 14 May 2016

On Android Marshmallow build on Wandboard Dual

This post will be edited as and when I have progress. The final post will be structured for easy reading.

I have upgraded my Ubuntu to 16.04 (Xenial) and I am having a host of problems compiling Marshmallow and the earlier Lollipop.

In Marshmallow I was getting the "Unsupported reloc error 42". The fix for this is provided here https://android-review.googlesource.com/#/c/223100/

Update the makefile as above and build the kernel. Apart from that try to build using a smaller parallel job option i.e. -j5 for a quad core. I seemed to get the "JACK server could not start" which might be because of high memory usage. Also increasing the swap memory helps. I used to have a 1GB of swap for my 4GB laptop and I used to compiler errors because of out of memory. When multiple instances of JACK starts running there would almost 2GB + of swap memory usage!

There is a problem with the SPL loader when the code is compiled using make. The board refuses to boot up. If the code is compiled manually i.e. ARCH=arm CROSS_COMPILE=prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi- make wandboard_defconfig etc. and I flash the SPL loader it boots. So this means there is something wrong with the compiler options used. Looking at the Makefile I find at line 974: BOOTLOADER_CROSS_TOOLCHAIN := `pwd`/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin/arm-linux-androideabi-

The problem above is that the toolchain used is wrong. This is why it refused to boot. Changing it to what I was doing normally the board booted up.

If you are using the OpenJDK 8 and you get Guava error as follows:

external/guava/guava/src/com/google/common/reflect/Types.java:317:
error: TypeVariableImpl is not abstract and does not override abstract 
method getAnnotatedBounds() in TypeVariable
 private static final class 
TypeVariableImpl<D extends GenericDeclaration>

The following updated code by google offers the solution.
https://android.googlesource.com/platform/external/guava/+/1bc06418bcf6355136e8f774092eac49805623b6%5E%21/#

Git clone it and checkout the commit id present in the link. Copy the Types.java file to the relevant place and start the compile.

Partitioning

Partitioning is same as lollipop. In the first boot partition we have the following files:
  • u-boot.img
  • zImage
  • imx6q-wandboard.dtb
  • imx6dl-wandboard.dtb
  • uenv.txt
  • uramdisk.img

The difference between lollipop and marshmallow for the wandboard is that the above files should be present in then root partition and not inside a separate /boot directory in the sdb1 partition.

The above can be easily changed but since we are talking about the stock kernel from wandboard I will not deviate.

Friday 8 April 2016

On Android development and porting

I have decided to work on parallel to learn to understand the android system and porting to a new SoC. My baremetal adventures will continue as is but this a slight distraction/relaxation from the intense work of the baremetal OS.

I will post articles and examples on what I have learnt in android along with some mini projects to demonstrate the concepts. I will referring to "Embedded Android" by Karim Yaghmour to learn my concepts. The development board which I will be using is a Wandboard dual with Bluetooth and WiFi. It has a NXP/Freescale i.MX6 dual core processor in it.

Sunday 3 April 2016

Code cleanup and refactoring in MDK-OS Clock setup

Clocks form an important part in any embedded system and configuration of this clock tree is very error prone. In the present code clean up I have parametrized the existing configurations which were hard coded. This is very error prone as any change in the base clock speed would cause a mismatch with the configuration.

The first step I took in refactoring my code was to have helper functions to get FCLK, HCLK and PCLK. In the same vein I created a conditional compilation set up which compiles based on the board i.e. it being a MINI2440 or a MINI2410 etc. From the clock point of view the crystal used in these boards varies. The MINI2440 uses a clock source derived from a crystal based on OM3 and OM2 pins. The crystal as per the schematic is a 12Mhz crystal.

With this as the base and using the helper functions the whole clock tree settings i.e the pre-scaler can be automated for different peripherals such as UART, SD MMC using formulae rather than hard coding values.

First we will try to understand the different clocks signals generated by the control logic. There are 3 clock signals generated FCLK for the CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.

The S3C2440 has  2 PLL's one for FCLK, HCLK and PCLK and the other dedicated for USB block (48 MHz). The control logic can make slow clocks without the PLL's.

What is a PLL and what does it do? PLL or a Phase Locked Loop is a control system which generates an output signal whose phase is related to the phase of the input signal.  Generally we use a PLL to generate a multiple of the input frequency. So the input to the PLL is a oscillator and output is a multiple of the input frequency. So in our case we have a 12MHz crystal oscillator which is given to the PLL's to generate multiples and keeping the phase locked with the input and output frequencies.
PLL's take time to stabilize. Hence there should be a way for the chip to work based on the oscillator frequency or an external signal. Once the PLL stabilizes and is able to generate a clean signal the chip can switch to the PLL frequency.

The following is the clock architecture of the S3C2440.


The main clock comes from the external crystal (XTlpll) or an external clock (EXTCLK). The clock generator includes an oscillator (Oscillation Amplifier), which is connected to an external crystal, and also has two PLL's (Phase locked loop) which generate the high frequency clock required in the S3C2440A.


 The OM[3:2] status is latched internally by referring the OM3 and OM2 pins at the rising edge of nRESET as shown below

According to the data sheet the clock selection during boot-up is Crystal for the main clock source and USB.

The MPLL  starts just after a reset but the MPLL output is not used as the system clock until the software writes valid settings to the MPLLCON register. Before these settings, the clock from the external crystal or EXTCLK source will be used as the system clock directly. Even if the user does not want to change the default value of the MPLLCON register, the user should write the same value into the MPLLCON register.

After the power on reset the crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the OSC (XTIpll) clock the PLL starts to operate according the default PLL configuration. However the PLL is commonly known to be unstable after power-on reset so Fin is fed directly to the FCLK instead of the Mpll (PLL output) before the software newly configures PLLCON.

The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.

The wave form diagram below gives a clearer picture


For USB clock control and USB device interface needs 48MHz clock hence a dedicated USB PLL (UPLL) generates the clock.

Now we come to coding the clock setup. The clock setup has to be parameterized.

We come to the init_clock(..) function. Here we set the clock lock time to maximum. Next we do a set_clock_divn(..). Here we set the dividers. We divide the FCLK by 1, HDIVN by 4 and PDIVN by 8. Note that MPLL is fed into the CLKCNTL logic which generates the FCLK.



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 set_clock_divn(CLK_BASE_ADDR,
     DIVN_UPLL_BY_1,
     HDIVN_FCLK_BY_4,
     PDIVN_HCLK_BY_2);


So the final clock setup would be:

 FCLK = 405 MHz.
 HCLK = 405/4 = 101MHz
 PCLK = 405/8 = 50 MHz

 We need to setup the CPU to asynchronous mode. We can see the P 2-11 of ARM920T (Chapter 5). Also S3C2440 does not support synchronous mode.

The code is as follows:


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__asm__ __volatile__(
  "mrc p15,0,r1,c1,c0,0\n\t"
  "orr r1,r1,#0xC0000000\n\t"
  "mcr p15,0,r1,c1,c0,0\n\t"
  : /* No output */
  : /* No input */
  : "r1" /* r1 clobbered */
  );

Next we have to set the 2 PLL's. MPLL and UPLL.

First we set the UPLL to generate 48 MHz as follows:



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 set_clk_upll(CLK_BASE_ADDR,0x38,0x2,0x2); //48 MHz.
    
 __asm__ __volatile__(
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
  );

Note the mov r0,r0. This is used generate at least 7 NOPs.

Next we set the MPLL to 405 MHz  as follows:



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 set_clk_mpll(CLK_BASE_ADDR,0x7f,0x2,0x1); //405 MHz

 __asm__ __volatile__(
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
   "mov r0,r0\n\t"
  );

Finally we clear the slow clock register bits as follows.


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#define clear_slow_clock(BA) do { \
 clear_reg_bits(CLKSLOW_REG(BA),UCLK_ON); \
 clear_reg_bits(CLKSLOW_REG(BA),MPLL_OFF); \
 __asm__ __volatile__ ( \
  "mov r0,r0 \n\t"  \
  "mov r0,r0 \n\t"  \
  "mov r0,r0 \n\t"  \
  "mov r0,r0 \n\t"  \
  "mov r0,r0 \n\t"  \
  "mov r0,r0 \n\t"  \
 ); \
 clear_reg_bits(CLKSLOW_REG(BA),SLOW_BIT); \
 } while(0)

We clear the UCLK bit to turn on UPL. Next we turn on the MPLL and allow it settle which takes 300us. Hence we have NOPs for the delay. After this we turn OFF the slow clock to set the MPLL to the FCLK.


To get the current clocks I have written utility functions so that I can derive the different clocks just by reading the registers itself.

First I have helper functions to get the dividers as follows:


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#define get_clk_pll_mdiv(PLL_REG) \
 (((readreg32(PLL_REG)) & MDIV_MASK) >> MDIV_SHIFT)

#define get_clk_pll_pdiv(PLL_REG) \
 (((readreg32(PLL_REG)) & PDIV_MASK) >> PDIV_SHIFT)

#define get_clk_pll_sdiv(PLL_REG) \
 (((readreg32(PLL_REG)) & SDIV_MASK) >> SDIV_SHIFT)

Next I get the 2 PLL clock i.e. UPLL and MPLL based on the following helper functions:


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uint32_t get_mpll_clk(uint32_t BA)
{
 uint32_t m,p,s;
 
 m = get_clk_pll_mdiv(MPLLCON_REG(BA)) + 8;
 p = get_clk_pll_pdiv(MPLLCON_REG(BA)) + 2;
 s = get_clk_pll_sdiv(MPLLCON_REG(BA));

 return ((m * S3C_CLOCK_REFERENCE) * 2)/(p * (1<<s));
}


uint32_t get_upll_clk(uint32_t BA)
{
 
 uint32_t m,p,s;
 
 m = get_clk_pll_mdiv(UPLLCON_REG(BA)) + 8;
 p = get_clk_pll_pdiv(UPLLCON_REG(BA)) + 2;
 s = get_clk_pll_sdiv(UPLLCON_REG(BA));

 return (m * S3C_CLOCK_REFERENCE)/(p * (1<<s));
}

To explain the above code I have to bring out the formulae. According the datasheet:

MPLL Control Register

Mpll = (2 * m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV

UPLL Control Register

Upll = (m * Fin) / (p * 2 S)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV



Hence we get the m, p and s.

Next we have the formula:

PLL Value Selection Guide (MPLLCON)
  1.  Fout = 2 * m * Fin / (p*(2^s) ), Fvco = 2 * m * Fin / p where: m=MDIV+8, p=PDIV+2, s=SDIV
  2.  600MHz ≤ FVCO ≤ 1.2GHz
  3.  200MHz ≤ FCLK OUT ≤ 600MHz
In the above code we return the Fout formula.

So to finally get the FCLK, HCLK,PCLK and the UCLK we have to check the dividers. We do divide the FCLK so we use Fout as is. Next for HCLK,PCLK and UCLK we have the following code:



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uint32_t get_hclk(uint32_t BA)
{
 uint32_t fclk = get_fclk(BA);

 switch(get_clock_hdivn(BA)) {
  case HDIVN_FCLK_BY_1:
   return fclk;
  case HDIVN_FCLK_BY_2:
   return (fclk >> 1);
  case HDIVN_FCLK_BY_4:
   //TODO: CAMDIVN conditon check pending.
   return (fclk >> 2);
  case HDIVN_FCLK_BY_3:
   //TODO: CAMDIVN conditon check pending.
   return (fclk / 3);
 }

 return fclk;
}

uint32_t get_pclk(uint32_t BA)
{
 uint32_t hclk = get_hclk(BA);

 switch(get_clock_pdivn(BA)) {
  case PDIVN_HCLK_BY_1:
   return hclk;
  case PDIVN_HCLK_BY_2:
   return hclk >> 1;
 }

 return hclk;
}

uint32_t get_uclk(uint32_t BA)
{
 uint32_t uclk = get_upll_clk(BA);

 switch(get_clock_upll_divn(BA)) {
  case DIVN_UPLL_BY_1:
   return uclk;
  case DIVN_UPLL_BY_2:
   return uclk >> 2;
 }

 return uclk;
}


Note that the FCLK forms the base for the HCLK i.e. we divide the FCLK to get the HCLK. Next for the PCLK, HCLK forms the base i.e. we divide the HCLK to get the PCLK.

For the UCLK we have the UPLL and hence we check the UDIVN and divide to get the final clock.

So there you have it. The clock setup for the S3C2440.

Time is an illusion
--Albert Einstein

Procuring and sourcing electronic components in India

The one thing that an embedded engineer needs is a lot of electronic components and boards and a decent low cost lab at home. I will write about my sources in procuring and sourcing components in India so that it helps others looking for answers to this.

The first thing that comes to mind for electronics enthusiasts in Bangalore is SP Road. Here you can get a lot of electronic components. I generally go to Vishal electronics but you should explore different shops and find what is needed and select what best fits you. Also do not forget to bargain. Before going there prepare a list and shop fast. The parking situation is horrible and your vehicle can get towed for no reason.

Some of the things you can buy in cheap for a small home lab setup are:
  1. Discrete components. (Resistors, capacitors, transistors, LED's etc). You would generally get through hole types but sometimes SMD components as well. There might be defective parts hence beware. Also since the handling of different components is really questionable be prepared for ESD issues in components.
  2. Soldering station and different solder tips.
  3. Magnifying glass. (Really need this to inspect your soldering and also seeing tiny parts in your PCB's).
  4. Cleaning alcohol solutions
  5. Cables, solder, solder paste  and solder braids (for de-soldering).
  6. Tweezers for holding the components in place while soldering so that you don't burn your fingers.
  7. Bread boards.
  8. Jumper cables. 
  9. Various interface cables such as RS232, USB to serial cables, Straight and cross cables etc. You get the choice of crimping done there.
I generally buy the above stuff in SP road. I generally tend to stay away from buying micro-controller’s or development boards from them because of poor handling but I have started looking at cheaper micro-controllers there.

Apart from this we have some pretty good online stores in India. Some of them are mentioned below:

  1. Tenet Technetronics ( http://tenettech.com  ) -- Slow delivery. I got my two MINI2440's from here. Apart from that I got myself a Nooelec SDR.
  2. Protocentral ( https://www.protocentral.com ) --  Fast delivery. Quite costly for simple items. You can find a lot of sparkfun and adafruit designs here.
  3. Kits 'n' spares ( http://kitsnspares.com ) -- You get element14 parts as element14 requires you to have a TIN number. Delivery is slow and also they are not organized. You have to follow up them with your orders or it will take a really long time for them to deliver. I got my MSP430 boards from here.
  4. Crazypi ( https://www.crazypi.com/ ) -- Misleading name as you would think they deal with only Raspberry Pi solutions. They deal with ARM SBC's. I got my  TI ARM Sitara based beaglebone from here. You can either go directly to their store or you can order from their website. Good service.
  5. Innovate solutions ( https://www.innovatesolutions.net/ ) -- Deals with ARM SBC's and microcontrollers, debuggers etc.  I got my i.MX6 based wandboard from here. You can also walk into their store to buy your items.
  6. Rhydo labz ( http://www.rhydolabz.com/ ) -- Personally I have not bought anything from here but heard they are good. You have a good selection of components and boards.
  7. Amazon -- Good passive kits such as resistors, capacitors and transistors
  8. Quad Store ( https://quadstore.in/ )  -- Very good collection for different sensors
For some of the boards I bought it directly from the vendor store or their partners. Some of them are:

  1. TI eStore ( https://store.ti.com/ ) -- Expensive and they only accept credit cards. Good board packaging so no worry about ESD's. Surprisingly fast delivery. I bought my MSP430 launchpads as well as MSP430 through hole package sample chips from them.
  2. Coreel Technologies ( http://www.coreel.com/ ) -- I bought a FPGA Digilent Basys 2 board from them. Expensive but they offer guarantees and warranties. Good packaging.

It is a good idea to invest some money on an oscilloscope. I have a Rigol  DS1102E two channel 100MHz oscilloscope. It is a really nice scope for a low price compared to a Tektronix or an Agilent. It costed me Rs 31500. You can buy it when they offer discounts. I bought it from Salicon Tech ( http://www.salicontech.com ). The prices are slightly expensive but the service is good. They provide after sales service provided you bear the cost. (Shipping + repair).

Apart from this you can always order free samples of different chips from different manufacturers and vendors to try it out in your designs. I got some free samples from FriendlyARM which I have detailed in my previous posts.

Apart from these have good relations with the vendor FAE's and always ask/bug them for development boards/parts whenever you meet them. They generally have some boards/chips lying around or they can offer you some refurbished boards or they will have connections which will allow you to get some boards/chips/parts at massive discounts.

Hope I have covered most of the things. I will edit this post from time to time if I find good vendors.

“Artists work best alone. Work alone.”
― Steve Wozniak,
iWoz

Friday 18 March 2016

Basic u-boot setup for porting

I have been doing some work on u-boot porting and I felt that I should write a small step by step guide for my reference.

  1. Pull the u-boot source from git repo.
  2. Create a separate branch. In this way you are creating
       isolating your changes to a separate branch. Once testing
       is done and is stable you can merge to the main branch.
       eg: git branch <yourbranchname> 
  3. Checkout to your branch.   eg: git checkout <yourbranchname> 
  4. Now we are ready to port u-boot to the new board. 
  5. Create a folder called <yourboardname> in board/vendor/
       eg: board/vendor/<yourboardname>
  6. Populate this folder with Kconfig,Makefile,<yourboardname>.c, any lds (linker script files) at a minimum.
    Modify Kconfig and Makefile accordingly. Any supporting files can be put in the above folder. 
  7. Create a configuration file in include/configs/<yourboardname>.h
  8. Create a defconfig file in configs/<yourboardname>_defconfig
  9. Edit arch/<cpu_architecture>/cpu/<cpu_architecture_variant>/<cpu_vendor>/Kconfig
        eg: arch/arm/cpu/armv7/mx6/Kconfig 
  10. Create a section TARGET_<yourboardname>
                        <...>
                        <...>
                        <...>
  11.  At the end of the file add the source path.
     eg: source "board/<vendor>/<yourboardname>/Kconfig"
  12.  Run
        CROSS_COMPILE="<yourcompilertoolchain>" make distclean
        CROSS_COMPILE="<yourcompilertoolchain>" make <yourboardname>_defconfig
        CROSS_COMPILE="<yourcompilertoolchain>" make
  13.  To flash the board with your new u-boot do:
        sudo dd if=u-boot.imx of=/dev/sdb bs=512 seek=2 conv=fsync

If you have a board similar to already existing boards use the configurations present
in the already existing board to jump start your changes.

No man should escape our universities without knowing how little he knows.
-J. Robert Oppenheimer
 





Saturday 20 February 2016

On job opportunities in bare metal programming.

A shameless plug,  if anybody needs to have bare metal firmware developed and need help in implementing it please leave a message. It would be great if you are hiring as I am open to good career opportunities.

USB Development on the S3C2440 update

Long time since my last post.  I had initially started off with the ethernet driver development but kept it pending due the lack of understanding of the timing diagrams. In its place I have started off with USB development. I will have a detailed write up once I have something going.

Thursday 28 January 2016

FriendlyARM Nano Pi2 review

I received two NanoPi2 samples from FriendlyARM somewhere around the first week of January. It took more than month to reach India from China using China Post. 

I was very excited about this as you would already know that I am developing a baremetal OS for the older mini2440. I had been informed that the mini2440 is out of production and in its place the newer and much smaller NanoPI with the S3C2451 chip is made available.

Just a few details about the NanoPi, it is a ARM9 S3C2451 chip running at 400Mhz with 64MB of DDR2. It has the usual interfaces as present in the S3C2440 based Mini2440 board.

Now coming to the NanoPi2 what is really impressive is the size of this thing. It has a size of 75mmx40mm. It is lesser than the size of a credit card approaching the size of a USB dongle.  FriendlyARM has done a real good job in making a board with such a small form factor.

The NanoPi2 comes packed with Samsung S5P 4418 Quad Core Cortex-A9 at 1.4G Hz with 1GB 32bit DDR3 RAM. As you would know for my baremetal programming I am mainly interested in the processor and RAM. Once I get this beast up, rest of the things follow much faster. There are two micro SD Slots, a USB 2.0 Host Type A, a micro USB for data input and power. It has 40 pin GPIO good enough for plenty of debugging.

It has pins for camera and LCD connections and HDMI output.

From the connectivity side it has Wifi and Bluetooth support with BLE4.0.

There is support for Linux (Debian Jessie) and Android (4.4.2) Kitkat.

 Now for the unboxing and setup. The NanoPi2 comes in a neat card board case. It looks like a wallet and is beautiful.



Side view of the beautiful card board case



Size comparison of the NanoPi2 with my meal pass card. It is really impressive.



The NanoPi2 connected to the PSU and RS232 board which is provided separately.





Finally I got this  cute NanoPi2 case to put into. I am not sure whether it is 3D printed but it sure looks like it. It looks like a cute soap box.




Debian Jessie running out of the box with the HDMI output connected to my monitor. You can also find my dear MINI2440 board photo bombing at the right side :)



This is a really neat evaluation board for Robotics, IoT with its Bluetooth and Wifi connectivity. Considering how small it is I think it also goes well with controlling of drones.
This is also a really good board for the maker community.

I am really excited in developing for this board especially to try to see if I can get my baremetal OS running on it.

Special thanks to Friendly ARM for gifting two samples of this board and kudos to them for making boards with such impressive form factor and functionality.

Simplicity is prerequisite for reliability. -- Edsger W. Dijkstra

Wednesday 27 January 2016

MINI2440 memory address banks and SDRAM setup.

Initially the loader can be booted up without setting the RAM. This is achieved by the stepping stone controller. This controller fetches first 4KB of data from the NAND flash and places it in the 4KB SRAM called the stepping stone buffer.


This SRAM is good enough for the loader to load the MDK OS. To do anything serious we need to setup the SDRAM.

My setup:

In my MINI2440 board I have two Samsung K4S561632N SDRAM chips each of size 32MB totalling 64MB of SDRAM.


To proceed further we need to understand the datasheet thoroughly.

From the datasheet we have:
    The K4S560432N / K4S560832N / K4S561632N is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits.
The SRAM type table is as follows:




Our memory being the K4S561632N its organization is 4 x 4,194,304 words by 16bits (i.e. 16M x 16). The x16 forms the data bus width i.e. 16 bits or 2 bytes. The "words" in the above sentence means this data bus width i.e. 16 bits. Hence the SDRAM outputs a "word".

Also here 268,435,456 bits is 32MB or 256Mb.

Notice that all the memories have "4 x " prefix. This is because all these memories  have 4 banks and therefore are 4 bank operation chips.

The organization in the data sheet is as follows for the 3 different memories:



In this case our memory organization is the 16Mx16 with Row Address from A0~A12 and Column Address from A0-A8.

Hence we can have 2^13 addressable rows and 2^9 addressable columns to make it 4194304 addressable words in each bank. Hence 4 banks x 4194304 addressable words become a total of 16777216 words. Since each word is 16 bits or 2 bytes the chip capacity is 32MB (=16777216 x 2 bytes (16 bits) = 33554432 or 32MB).

Similarly we can figure out the numbers for the other 2 memories.

For the K4S560832N:
4 x 8,388,608 words = 33554432 words.
Since it is 8 bits per word or 1 byte per word it is 33554432 x 1 = 33554432 or 32MB.

For the K4S560432N:
4 x 16,777,216 = 67108864 words.
Since it is 4 bits per word or 1/2 a byte per word it is 67108864 x 1/2 = 33554432 or 32MB.


Now we come to how these memory chips are wired to our processor. A diagram of how the chips are wired to the processor is below (ASCII art courtesy of Juergen Borleis of Pengutronix mailing list for helping me understand the bank map configuration):

----------+      /CS to bank#2
          |----------------------------------------------------------
          |                                            |            |
S3C2440   |      /CS to bank#1                         |            |
          |------------------------------              |            |
          |                  |          |              |            |
          |             +--------+  +--------+     +--------+   +--------+
          |             | SDRAM1 |  | SDRAM2 |     | SDRAM3 |   | SDRAM4 |
          |             |        |  |        |     |        |   |        |
          |             +--------+  +--------+     +--------+   +--------+
          |            0..15 |          |16..31   0..15|            |16..31
          |                  |          |              |            |
          |----------------------------------------------------------
          |  32 bit databus
          |
----------+


If we go back to schematic we can find that nGCS6 with net name LLnSCS0 is connected to nSCS (SDRAM Chip Select) input of the two 32 MB chips.




Coming back to the data sheet we see that nGCS6 starts at memory address 0x30000000. Hence our SDRAM memory address starts from 0x30000000. The snapshot of the memory map is below:

According to the data sheet the nGCS6 forms Bank 6. Hence the two SDRAM chips are connected to Bank6 with both 16 bit bus width forming connected to the 32 bit data bus of the processor. You can verify this in the schematic snapshot below:



 You can see that the LDATA0 to LDATA15 connections from chip1 and LDATA16 to LDATA31 from chip2 forming the 32 bit data bus width.

When an address say 'A' is sent on the address lines for a read from the address then the chip U6 will respond with the data set in address 'A' through LDATA0 - LDATA15. Since the same address lines are fed to chip U7 it too responds with the data set in address 'A' through LDATA16 - LDATA31. When a write is done to address 'A', the first 16 bit data is set in the address 'A' of chip U6 and the send 16 bit data is set in address 'A' of chip U7.

Notice that the address pin connections start at ADDR2. For a 32 bit data bus the address is at 4 byte boundaries.


Notice that LADDR24 and LADDR25 lines are set as inputs to BA0 and BA1 respectively. BA0 and BA1 forms bank select pins for the chip.

Now why is LADDR24 and LADDR25 pins selected? 
  1. There are 4 banks per chip. Hence the 2 bit combination will allow to select the 4 banks.
  2. If the bits below LADDR24 are set to 1 it becomes 0xFFFFFF which is 16777215(starting from 0) which is the size of the 4 banks. (4 x4M words). Since the address starts at LADDR2 shift the LADDR24 and LADDR25 by 2 bits to the right. Now we get 0x3FFFFF which is 4194303 (starting from 0) which is the size of the single bank. A 4194304 address switches the bank to 1.  Hence as far as I see this is the explanation for the bank switching using the addresses themselves i.e. when the bits of the addresses corresponding to banks change there is a bank switch.

Register setup:

We finally come to source code for the SDRAM setup. 
First we need to configure Bus Width and Wait Control register (BWSCON)
The code is as follows:

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void config_bwscon()
{

 /* Configure BWSCON */
 writereg32(BWSCON_REG(MEM_BA),
   DW7_RESERVED|DW6_32b|DW5_RESERVED|DW4_RESERVED|
   DW3_RESERVED|DW2_RESERVED|DW1_RESERVED);
}

Here the DW6 parameter is set to DW6_32b i.e. bus width as 32 bit.

My SDRAM init is as follows:

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void sdram_init()
{

 config_bwscon();

 /* Configure BANKCON6/BANKCON7 */
 writereg32(BANKCON6_REG(MEM_BA),MT_SYNC_DRAM|SCAN_9BIT);

 /* 
  * Set BANKCON7 to ROM/SRAM i.e 00 and not SYNC_DRAM.
  * Rest of the values should not be used as they are reserved
  * Default value is SYNC_DRAM which should not be used.
  */
 writereg32(BANKCON7_REG(MEM_BA),MT_ROM_SRAM);

 /* Configure SDRAM Refresh settings */
 writereg32(REFRESHCTL_REG(MEM_BA),REFEN|Tsrc_5|1269);

 /* Configure Banksize setting */
 writereg32(BANKSIZE_REG(MEM_BA),BURST_EN|SCKE_EN|SCLK_EN|BK76MAP_64MB);

 /* Configure mode set register for BANK6 */
 writereg32(MRSRB6_REG(MEM_BA),CAS_LATENCY_2CLK);

 return;
}

I set the BANKCON6 register to Sync DRAM as it is SDRAM (Synchronous DRAM). For the memory type of SDRAM I set SCAN parameter to SCAN_9BIT as it is A0-A8 or 9 bit.

Bank7  has to be disabled. Set the BANKCON7 register to MT_ROM_SRAM as it is set default to MT_SYNC_DRAM which should be removed.

There is Trcd or RAS to CAS delay to set. In the datasheet the RAS to CAS latency or Trcd(min) is 20ns. In our processor we have setup the HCLK to be 101 Mhz or 9.99ns ~ 10ns. Hence we have to setup or Trcd to have to 2 clock delay which is 00.

Refresh control register (REFRESH):
We set REFEN which is self auto refresh.
We set TREFMD to 0 CBR/Auto refresh mode.
We set the SDRAM RAS pre-charge time to 2 clocks i.e. value 00 as the data sheet gives a tRP(min) as 20ns or 2 clock cycles.
We set the SDRAM semi row cycle time Tsrc to Tsrc_5. The calculation is as follows:

Trc = Tsrc + Trp
or
Tsrc = Trc - Trp

From the data sheet we have Trc as 65ns Trp as 20 ns. Hence we get Tsrc as 45ns. Hence we set Tsrc_5 which is 5 clocks or 50ns.

I set the refresh counter to 1269 as given in the data sheet example.

Banksize register settings (BANKSIZE):
Here I enable BURST_EN(burst enable), SCKE_EN (SDRAM power down mode enable), SCLK_EN (SCLK being enabled during SDRAM access cycle to reduce power consumption) and BANK76MAP set to 001 or 64MB as the size of the memory is 32MiB + 32MiB = 64MiB.

SDRAM Mode register set register (MRSR):
We simply set the CL parameter or the CAS Latency to 2 clocks. According to the data sheet the CAS latency is 2.

 A note on the memory controller bank select:

The S3C2440 has 8 memory banks. The General Chip select or nGCS should be connected to the different chip selects of the various peripherals connected which use the address space.
The banks are activated when the address of a memory is within the address region of the bank. This takes the burden out of doing a chip select manually whenever you want to access the memory region. Hence you can multiplex the address lines to different chips in different banks. When an address is generated the chip in the memory region is automatically selected using the bank chip select signal. I will verify this and provide an oscilloscope trace.

For reference from the data sheet:





Conclusion:
We do all the SDRAM setup in the loader itself as the MDK OS is loaded onto the SDRAM.

References: http://thread.gmane.org/gmane.comp.embedded.ptxdist.oselas.community/1994/focus=2010

Schematics from FriendlyARM.
Data sheet snapshots from Samsung S3C2440 data sheet.
Memory organization snap shots from Samsung K4S561632N data sheet.

It is better to do the right problem the wrong way than the wrong problem the right way.  --Richard Hamming

Thursday 7 January 2016

Notes on Linux virtual memory page walk.

A simple test of virt_to_phys translation and accessing of physical RAM

I wanted to test the actual writing of a value on the physical RAM.

Hardware is a S3C2440 or a Wandboard.

Create a module and use virt_to_phys(mem). The "mem" should be pointing to the
memory address allocated using kmalloc(..). Print the value and note it down. Hit
the reset switch. When the bootloader boots up print the location using md.b <addr> 1.

The value should be present on that particular location.

Some statistics on the S3C2440:


PAGE_OFFSET             0xC0000000
PLATFORM_PHYS_OFFSET     0x30000000  --> The actual starting physical memory.
                                        The memory map says that it starts from 0x30000000

The calculation of the physical address is from the formula:

PHYSICAL_ADDRESS = KERNEL_VIRTUAL_ADDRESS - PAGE_OFFSET + PLATFORM_PHYS_OFFSET.

Explanation for the above formula:

The kernel virtual address starts from 0xC0000000. To get to the physical address with base '0' subtract it from
the PAGE_OFFSET. To get to the actual physical address based on the memory mapped address add it with the
PLATFOR_PHYS_OFFSET.

Bootup physical and virtual memory setup.

The paging unit startup is present in arch/arm/kernel/head.S

The kernel virtual RAM addr is based on the formula KERNEL_RAM_VADDR = PAGE_OFFSET + TEXT_OFFSET

The TEXT_OFFSET starts off at 0x00008000 which is defined in arch/arm/Makefile as TEXT_OFFSET := $(textofs-y)
where textofs-y := 0x00008000. Therefore the KERNEL_RAM_VADDR starts at 0xC0008000

The swapper_pg_dir starts off at (KERNEL_RAM_VADDR - PG_DIR_SIZE) where PG_DIR_SIZE is 0x4000. So the value is
0xC0008000 - 0x4000 = 0xC0004000. The swapper_pg_dir is the virtual address of the initial page table.

Initial page tables are setup with r8 having the phys_offset, r9 with cpuid and r10 the processor info.
It returns r4 which contains the physical page table address.

Initially an identity mapping is done i.e. the virtual address will have the same physical address. This will
later be removed once the kernel starts up fully.
The i/o space is also mapped so that the UART can be used before the paging unit is initialized.

Virtual memory for address space.


Glossary:

Page Frames -> Physical pages. Each page frame contains a page i.e. length of page frame coincides with a page.
Page -> A block of data that is stored in a page frame or disk.
pgd -> Page global directory.
pmd -> Page middle directory.
pte -> Page table entry.

1) Each process has a structure associated with it called mm_struct(include/linux/mm_types.h). Like a process list the
   mm_struct of each process are linked together as a linked list.
2) Each process has a pgd,pmd and a pte associated with it.
3) If a region is backed by a file, its vm_file (include/linux/fs.h) field will be set in "struct vm_region".
   By traversing vm_file->f_dentry->d_inode->i_mapping,(linux/path.h,linux/dcache.h,linux/fs.h,linux/fs.h) the
   associated address_space for the region may be obtained using the address_space_operations a_ops field. This
   structure has all the filesystem specific information required to perform page-based operations on disk. This
   structure is the address_space_operations which contains writepage,readpage etc. methods.
4) Initial parent mm_struct is initialized using INIT_MM_CONTEXT macro in mm/init-mm.c
5) A thread can be identified in the task list by finding all "task_structs" that have pointers to the same mm_struct.
6) Each memory region is respresented by a "vm_area_struct", which never overlaps. A full list of mapped regions that a
   process has may be viewed using the proc interface at /proc/PID/maps.
7) VMA supports vma operations using the "vm_operations_struct" using the methods open(),close() and nopage().
8) mmap() is used to create new memory regions within a process. *DOUBT* Initial memory regions and initial process exec.

The pgd,pmd and pte are allocated in the kernel space. Verified by checking the address which is 0xC0000000 plus.(This is obvious).

** Each task's "thread_info" structure is allocated at the endo of its stack. The task element of the structure is a pointer to the
task's actual task_struct.(Ref: Linux Kernel Development book. Chapter 3 Pg 27) **

It is useful to be able to quickly look up the process descriptor of the currently executing task, which is done via current macro.

Exercise:

1) Given a process number traverse the mm_struct list and dump the pgd address.


I have written a rough test module for my understanding.



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#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/cdev.h>
#include <linux/thread_info.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <linux/spinlock.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>

#define CLASS_NAME "processmemtest"
#define DEV_FNAME "PROCESSMEMTESTMOD"
#define DEV_COUNT 1

/*
 * Objective:
 * 1) Given a process number traverse the mm_struct list
 *  and dump the pgd address.
 *
 * Bonus
 * -----
 * 2) Create a debugfs file and dump the neccessary debug information to it.
 * 3) Extract the pgd for each task.
 */


/*
 * Design:
 * -------
 * Create an attribute file and use it to write the process
 * number to it. Use it to traverse the mm_struct list and 
 * display the pgd address either in the attribute file or
 * in dmesg.
 */

/*
 *
 */

static ssize_t process_mem_test_read(
       struct file *file, 
       char __user *buff,
       size_t count,
       loff_t *offset
        ) 
{
 printk(KERN_ALERT "Process mem test read\n");

 return 0; //Make the user space process exit read.
}

static ssize_t process_mem_test_write(
       struct file *file,
       const char __user *buff,
       size_t count,
       loff_t *offset)
{
 printk(KERN_ALERT "Process mem test write\n");

 return count;
}

static int process_mem_test_open(
     struct inode *inode,
     struct file *file
     )
{
 printk(KERN_ALERT "Process mem test open\n");
 return 0;
}

static int process_mem_test_release(
     struct inode *inode,
     struct file *file
     )
{
 printk(KERN_ALERT "Process mem test release\n");
 return 0;
}
         
struct file_operations process_mem_test_fops = {
 .owner = THIS_MODULE,
 .read = process_mem_test_read,
 .write = process_mem_test_write,
 .open = process_mem_test_open,
 .release = process_mem_test_release,
};


dev_t process_mem_test_dev_no;

struct process_mem_test_device {
 struct cdev cdev;
} process_mem_test_dev;

struct class *process_mem_test_class;
struct device *process_mem_test_dev_info;


ssize_t process_mem_test_attr_show(struct device *dev, 
     struct device_attribute *attr,
     char *buf)
{
 struct task_struct *current_task;
 struct vm_area_struct *vmarea_struct_addr;

 current_task = current;


 if(current_task != NULL) {
  printk(KERN_ALERT "Current task : %d",
        current_task->pid);
  /*printk(KERN_ALERT "Current task : %d, On CPU %d\n",
     current_task->pid,current_task->on_cpu);*/
  printk(KERN_ALERT "mm: 0x%lx, active_mm 0x%lx\n",
     (unsigned long)current_task->mm,
     (unsigned long)current_task->active_mm);
  printk(KERN_ALERT "Page global directory : 0x%lx\n",
     (unsigned long)current_task->mm->pgd);
  printk(KERN_ALERT "mmap base : 0x%lx",
    (unsigned long)current_task->mm->mmap_base);

  vmarea_struct_addr = current_task->mm->mmap;

  while(vmarea_struct_addr != NULL) {
   
   printk(KERN_ALERT "vm_start : 0x%lx, vm_end : 0x%lx\n",
       (unsigned long)vmarea_struct_addr->vm_start,
       (unsigned long)vmarea_struct_addr->vm_end);
   vmarea_struct_addr = vmarea_struct_addr->vm_next;
  }


 } else {
  printk(KERN_ALERT "Current task NULL\n");
 }

 return sprintf(buf,"attrib show\n");
}


void my_follow_page(struct mm_struct *mm,
     unsigned long addr_res)
{
 pgd_t *pgd;
 pmd_t *pmd;
 pud_t *pud;
 pte_t *ptep, pte;
 unsigned long pfn;

 struct page *page;
// char byte_val = 0;

 down_read(&(mm->mmap_sem));

 pgd = pgd_offset(mm,addr_res);

/* copy_from_user(&byte_val,addr_res,1);
 printk(KERN_ALERT "virt addr: 0x%lx, byte val : 0x%lx\n",
       addr_res,
       byte_val);*/

 if(pgd_none(*pgd) || pgd_bad(*pgd)) {
  printk(KERN_ALERT "pgd bad\n");
  return;
 } else {
  printk(KERN_ALERT "pgd 0x%lx\n",(unsigned long)pgd);
 }

 pud = pud_offset(pgd,addr_res);
 
 if(pud_none(*pud) || pud_bad(*pud)) {
  printk(KERN_ALERT "pud bad\n");
  return;
 } else {
  printk(KERN_ALERT "pud 0x%lx\n",(unsigned long)pud);
 }

 pmd = pmd_offset(pud,addr_res);

 if(pmd_none(*pmd) || pmd_bad(*pmd)) {
  printk(KERN_ALERT "pmd bad\n");
  return;
 } else {
  printk(KERN_ALERT "pmd 0x%lx\n",(unsigned long)pmd);
 }

 
 ptep = pte_offset_map(pmd,addr_res);
 if(!ptep) {
  printk(KERN_ALERT "ptep bad\n");
 } else {
  printk(KERN_ALERT "ptep 0x%lx\n",(unsigned long)ptep);
 }

 pte = *ptep;
 

 if(pte_present(pte)) {
  printk(KERN_ALERT "pte : 0x%lx\n",(unsigned long)pte);
  page = pte_page(pte);
 } else {
  printk(KERN_ALERT "pte not present\n");
 }

 printk(KERN_ALERT "pte with offset 0x%lx offset : 0x%lx\n",
   pte+((addr_res) & ((1<<PAGE_SHIFT)-1)),
   addr_res & ((1<<PAGE_SHIFT)-1));

 
 printk(KERN_ALERT "pfn from pte : 0x%lx\n",pfn = pte_pfn(pte));

 printk(KERN_ALERT "pfn to addr : 0x%lx, addr_res : 0x%lx\n",(pfn<<PAGE_SHIFT), 
     (unsigned long)PAGE_MASK);

 printk(KERN_ALERT "phys_addr : 0x%lx\n",(pfn<<PAGE_SHIFT) + (addr_res & ~PAGE_MASK));

 up_read(&(mm->mmap_sem));
}

//#define LOCK_TEST
#undef LOCK_TEST

#define MAP_REGION 0x100000

ssize_t process_mem_test_attr_store(struct device *dev, 
      struct device_attribute *attr,
      const char *buf,
      size_t count)
{

 struct task_struct *current_task;
 unsigned long addr_res;
 struct vm_area_struct *vmarea_struct_addr;
 unsigned int i = 0;

#ifdef LOCK_TEST
 DEFINE_SPINLOCK(test_lock);
 spin_lock_irq(&test_lock);
#endif

 current_task = current;

 if(current_task != NULL) {

  printk(KERN_ALERT "\nCurrent task pid: %d\n",
        current_task->pid);

  printk(KERN_ALERT "mm: 0x%lx, active_mm 0x%lx\n",
      (unsigned long)current_task->mm,
      (unsigned long)current_task->active_mm);
  printk(KERN_ALERT "Page global directory : 0x%lx\n",
      (unsigned long)current_task->mm->pgd);
  printk(KERN_ALERT "mmap base : 0x%lx",
      (unsigned long)current_task->mm->mmap_base);

  vmarea_struct_addr = current_task->mm->mmap;

  while(vmarea_struct_addr != NULL) {
   printk(KERN_ALERT "vm_start : 0x%lx, vm_end : 0x%lx\n",
       (unsigned long)vmarea_struct_addr->vm_start,
       (unsigned long)vmarea_struct_addr->vm_end);

   vmarea_struct_addr = vmarea_struct_addr->vm_next;
  }


 } else {
  printk(KERN_ALERT "Current task NULL\n");
 }

 if(kstrtol(buf,10,&addr_res) != 0) {
  printk(KERN_ALERT "Error converting to long\n");
  return count;
 }

// copy_from_user(&kval,(unsigned int *)addr_res,4);

// printk(KERN_ALERT "kval : %x\n",kval);
 
 //addr_res = MAP_REGION;

 printk(KERN_ALERT "addr: 0x%lx\n",addr_res);


 my_follow_page(current_task->mm,
      addr_res+i);
     
#ifdef LOCK_TEST
 while(1)
  ;

 printk(KERN_ALERT "After lock\n");

#endif

 return count;
}

#define TEST_SIZE 4LL
int test_arr[TEST_SIZE] = {5,4,3,2};

/*
 * Explanation for the below code
 *
 * Initially "start" is called. Do all init's,holding locks in this
 * function. After this "show" is called. This is right after "start"
 * and is the first iteration. After this "next" is called where
 * we increment the iterator. After this "show" is called. If in 
 * "next" we reach the end we return NULL. This triggers the call to
 * "stop". A call will be done to start again where *pos is checked
 *  and return NULL which exits the sequence.
 *
 * General Sequence:
 * -----------------
 *  Start -> Show -> Next -> Show -> Next ->.. Next-> Stop-> Start-> Stop.
 */


unsigned char STOP_FLAG = 0;
void * mem_dbg_start(struct seq_file *m, loff_t *pos)
{
 struct vm_area_struct *vmarea_struct_addr;

 printk(KERN_ALERT "[GAUN] In %s\n",__FUNCTION__);

 if(STOP_FLAG) {
  STOP_FLAG = 0;
  return NULL;
 }

 if(current == NULL)
  return NULL;

 vmarea_struct_addr = current->mm->mmap;

 if(vmarea_struct_addr == NULL)
  return NULL;

 seq_printf(m,"Current task : %d\n",
     current->pid);
 seq_printf(m,"mm: 0x%lx, active_mm 0x%lx\n",
    (unsigned long)current->mm,
    (unsigned long)current->active_mm);
 seq_printf(m,"Page global directory : 0x%lx\n",
    (unsigned long)current->mm->pgd);
 seq_printf(m,"mmap base : 0x%lx\n",
    (unsigned long)current->mm->mmap_base);

 return vmarea_struct_addr;

 /*printk(KERN_ALERT "In %s pos : %lld\n",__FUNCTION__,*pos);
 
 if((*pos) == TEST_SIZE)
  return NULL;

 return test_arr;*/
}

void * mem_dbg_next(struct seq_file *m, void *v, loff_t *pos)
{

 struct vm_area_struct *vmarea_struct_addr;

 vmarea_struct_addr = (struct vm_area_struct *)v;

 vmarea_struct_addr = vmarea_struct_addr->vm_next;

 if(vmarea_struct_addr == NULL) {
  STOP_FLAG = 1;
  return NULL;
 }

 return vmarea_struct_addr;

/* (*pos)++;

 if((*pos) == TEST_SIZE) {
  printk(KERN_ALERT "[GAUN] Match\n");
  return NULL;
 }
 
 printk(KERN_ALERT "In %s pos : %lld\n",__FUNCTION__,*pos);
 return test_arr+(*pos);*/
}

int mem_dbg_show(struct seq_file *m, void *v)
{
 struct vm_area_struct *vmarea_struct_addr;

 vmarea_struct_addr = (struct vm_area_struct *) v;

 printk(KERN_ALERT "[GAUN] In %s\n",__FUNCTION__);


 if(vmarea_struct_addr != NULL)
  seq_printf(m,"vm_start : 0x%lx, vm_end : 0x%lx\n",
     (unsigned long)vmarea_struct_addr->vm_start,
     (unsigned long)vmarea_struct_addr->vm_end);
/* if(v != NULL)
  seq_printf(m,"%x ",*((int *)v));*/

 return 0;
}

void mem_dbg_stop(struct seq_file *m, void *v)
{
 printk(KERN_ALERT "[GAUN] In %s\n",__FUNCTION__);
}

static const struct seq_operations seq_dbg_ops = {
 .start = mem_dbg_start,
 .next = mem_dbg_next,
 .stop = mem_dbg_stop,
 .show = mem_dbg_show,
};


int process_mem_dbg_open(struct inode *inode,
     struct file *file) 
{
 return seq_open(file,&seq_dbg_ops);
}

static const struct file_operations process_mem_dbg_fops = {
 .open = process_mem_dbg_open,
 .read = seq_read,
 .llseek = seq_lseek,
 .release = seq_release,
};

DEVICE_ATTR(
   process_mem_test,
   S_IRWXU|S_IRWXG|S_IRWXO,
   process_mem_test_attr_show,
   process_mem_test_attr_store
   );

struct dentry *process_mem_dir;
struct dentry *process_mem_dbgfile;

static int __init process_mem_test_init(void)
{
 int retval = 0;


 printk(KERN_ALERT "Process mem test init\n");

 retval = alloc_chrdev_region(
      &process_mem_test_dev_no,
      0,
      DEV_COUNT,
      DEV_FNAME
      );

 if(retval == 0) {
  printk(KERN_ALERT "Allocated char region with Major number : %d, Minor number : %d\n", 
    MAJOR(process_mem_test_dev_no),
    MINOR(process_mem_test_dev_no));
 } else {
  printk(KERN_ALERT "Could not allocate char region\n");
  return retval;
 }
 
 cdev_init(&(process_mem_test_dev.cdev),
   &process_mem_test_fops);
 
 process_mem_test_dev.cdev.owner  = THIS_MODULE;

 retval = cdev_add(&process_mem_test_dev.cdev,
    process_mem_test_dev_no,DEV_COUNT);

 if(retval != 0) {
  printk(KERN_ALERT "Could not add character device\n");
  return retval;
 }
 
 process_mem_test_class = class_create(THIS_MODULE,CLASS_NAME);
 process_mem_test_dev_info = device_create(
     process_mem_test_class,
     NULL,
     process_mem_test_dev_no,
     NULL,
     "process_mem_test_dev_0"
     );


 retval = device_create_file(
     process_mem_test_dev_info,
     &dev_attr_process_mem_test
     );
    
 if(retval != 0) {
  printk(KERN_ALERT "Could not create device file\n");
  return retval;
 }

 process_mem_dir = debugfs_create_dir(
      "process_mem_dbg",
      NULL);

 
 if(process_mem_dir == NULL) {
  printk(KERN_ALERT 
    "Could not create directory in debugfs\n");
 } else {
  process_mem_dbgfile = debugfs_create_file(
        "process_mem_test",
        0600,
        process_mem_dir,
        NULL,
        &process_mem_dbg_fops);
 }

 return 0;
}

static void __exit process_mem_test_exit(void)
{
 printk(KERN_ALERT "Process mem test exit\n");

 unregister_chrdev_region(process_mem_test_dev_no,
      DEV_COUNT);

 device_destroy(process_mem_test_class,
      process_mem_test_dev_no);

 class_destroy(process_mem_test_class);

 cdev_del(&process_mem_test_dev.cdev);

 debugfs_remove(process_mem_dbgfile);
 debugfs_remove(process_mem_dir);

}


module_init(process_mem_test_init);
module_exit(process_mem_test_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("TEST");
MODULE_DESCRIPTION("Process mem test");

The output log file captured is as follows:



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root@pathfinder:~# insmd   od process_mem_test.ko 
[   87.482043] Process mem test init
[   87.482164] Allocated char region with Major number : 250, Minor number : 0
root@pathfinder:~# [  109.271821] 
[  109.271821] Current task pid: 2392
[  109.271916] mm: 0xc3b35c00, active_mm 0xc3b35c00
[  109.275625] Page global directory : 0xc3af4000
[  109.279979] mmap base : 0xb6fc4000
[  109.283138] vm_start : 0x8000, vm_end : 0x9000
[  109.287658] vm_start : 0x10000, vm_end : 0x11000
[  109.292181] vm_start : 0xb6e60000, vm_end : 0xb6f89000
[  109.297215] vm_start : 0xb6f89000, vm_end : 0xb6f90000
[  109.302250] vm_start : 0xb6f90000, vm_end : 0xb6f92000
[  109.307284] vm_start : 0xb6f92000, vm_end : 0xb6f93000
[  109.312319] vm_start : 0xb6f93000, vm_end : 0xb6f96000
[  109.317355] vm_start : 0xb6f9e000, vm_end : 0xb6fbb000
[  109.322390] vm_start : 0xb6fbe000, vm_end : 0xb6fc1000
[  109.262697] vm_start : 0xb6fc1000, vm_end : 0xb6fc2000
[  109.267731] vm_start : 0xb6fc2000, vm_end : 0xb6fc3000
[  109.272766] vm_start : 0xb6fc3000, vm_end : 0xb6fc4000
[  109.277801] vm_start : 0xbec00000, vm_end : 0xbec22000
[  109.282841] kval : 1234
[  109.285221] addr: 10830
[  109.287612] pgd 0xc3af4000
[  109.290257] pud 0xc3af4000
[  109.292903] pmd 0xc3af4000
[  109.295548] ptep 0xc2e17040
[  109.298279] pte : 0x322d814f
[  109.301097] pte with offset 0x322d897f offset : 0x830



U-Boot 1.3.2-mini2440 (Feb 24 2014 - 23:40:48)


I2C:   ready

DRAM:  64 MB

NOR Flash not found. Use hardware switch and 'flinit'

Flash:  0 kB

NAND:  256 MiB

Found Environment offset in OOB..

USB:   S3C2410 USB Deviced

In:    serial

Out:   serial

Err:   serial

MAC: 08:08:11:18:12:27

Hit any key to stop autoboot:  3     0 

MINI2440 # md.b 0x322d814f 1000   0         500

322d814f: 00 01 00 00 00 47 4e 55 00 00 00 00 00 02 00 00    .....GNU........

322d815f: 00 06 00 00 00 1a 00 00 00 04 00 00 00 14 00 00    ................

322d816f: 00 03 00 00 00 47 4e 55 00 11 ef 02 49 29 da 5d    .....GNU....I).]

322d817f: 6a 2e df 8b 7d 02 2f a5 3d cb e0 f3 e7 03 00 00    j...}./.=.......

322d818f: 00 0b 00 00 00 09 00 00 00 02 00 00 00 08 00 00    ................

322d819f: 00 00 00 00 00 00 00 00 00 0a 00 00 00 06 00 00    ................

322d81af: 00 00 00 00 00 04 00 00 00 05 00 00 00 01 00 00    ................

322d81bf: 00 03 00 00 00 07 00 00 00 00 00 00 00 03 00 00    ................

322d81cf: 00 02 00 00 00 02 00 00 00 06 00 00 00 00 4a 21    ..............J!

322d81df: 38 88 40 a0 21 02 00 00 00 04 00 00 00 0a 00 00    8.@.!...........

322d81ef: 00 9c bb 93 1c 0b 0f b5 a5 b8 2b 6b 15 e2 41 72    ..........+k..Ar

322d81ff: f0 76 d7 9b 7c 50 b5 a8 10 7c ed 11 0f 5b 9a 3b    .v..|P...|...[.;

322d820f: 0f 2f 4e 3d f6 00 00 00 00 00 00 00 00 00 00 00    ./N=............

322d821f: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00    ................

322d822f: 00 20 00 00 00 28 00 00 00 18 84 00 00 00 00 00    . ...(..........

322d823f: 00 12 00 00 00 1a 00 00 00 30 84 00 00 00 00 00    .........0......

322d824f: 00 12 00 00 00 1b 00 00 00 dc 83 00 00 00 00 00    ................

322d825f: 00 12 00 00 00 2f 00 00 00 e8 83 00 00 00 00 00    ...../..........

322d826f: 00 12 00 00 00 3d 00 00 00 0c 84 00 00 00 00 00    .....=..........

322d827f: 00 12 00 00 00 54 00 00 00 24 84 00 00 00 00 00    .....T...$......

322d828f: 00 12 00 00 00 22 00 00 00 3c 84 00 00 00 00 00    ....."...<......

322d829f: 00 12 00 00 00 37 00 00 00 48 84 00 00 00 00 00    .....7...H......

322d82af: 00 12 00 00 00 42 00 00 00 f4 83 00 00 00 00 00    .....B..........

322d82bf: 00 12 00 00 00 00 5f 5f 67 6d 6f 6e 5f 73 74 61    ......__gmon_sta

322d82cf: 72 74 5f 5f 00 6c 69 62 63 2e 73 6f 2e 36 00 73    rt__.libc.so.6.s

322d82df: 70 72 69 6e 74 66 00 61 62 6f 72 74 00 73 74 72    printf.abort.str

322d82ef: 6c 65 6e 00 67 65 74 63 68 61 72 00 63 6c 6f 73    len.getchar.clos

322d82ff: 65 00 6f 70 65 6e 00 5f 5f 6c 69 62 63 5f 73 74    e.open.__libc_st

322d830f: 61 72 74 5f 6d 61 69 6e 00 77 72 69 74 65 00 47    art_main.write.G

322d831f: 4c 49 42 43 5f 32 2e 34 00 00 00 00 00 02 00 02    LIBC_2.4........

322d832f: 00 02 00 02 00 02 00 02 00 02 00 02 00 02 00 00    ................

322d833f: 00 01 00 01 00 10 00 00 00 10 00 00 00 00 00 00    ................

322d834f: 00 14 69 69 0d 00 00 02 00 5a 00 00 00 00 00 00    ..ii.....Z......

322d835f: 00 24 08 01 00 15 01 00 00 fc 07 01 00 16 04 00    .$..............

322d836f: 00 00 08 01 00 16 05 00 00 04 08 01 00 16 0a 00    ................

322d837f: 00 08 08 01 00 16 01 00 00 0c 08 01 00 16 06 00    ................

322d838f: 00 10 08 01 00 16 02 00 00 14 08 01 00 16 07 00    ................

322d839f: 00 18 08 01 00 16 03 00 00 1c 08 01 00 16 08 00    ................

322d83af: 00 20 08 01 00 16 09 00 00 10 40 2d e9 33 00 00    . ........@-.3..

322d83bf: eb 10 40 bd e8 1e ff 2f e1 04 e0 2d e5 04 e0 9f    ..@..../...-....

322d83cf: e5 0e e0 8f e0 08 f0 be e5 18 84 00 00 00 c6 8f    ................

322d83df: e2 08 ca 8c e2 18 f4 bc e5 00 c6 8f e2 08 ca 8c    ................

322d83ef: e2 10 f4 bc e5 00 c6 8f e2 08 ca 8c e2 08 f4 bc    ................

322d83ff: e5 00 c6 8f e2 08 ca 8c e2 00 f4 bc e5 00 c6 8f    ................

322d840f: e2 08 ca 8c e2 f8 f3 bc e5 00 c6 8f e2 08 ca 8c    ................

322d841f: e2 f0 f3 bc e5 00 c6 8f e2 08 ca 8c e2 e8 f3 bc    ................

322d842f: e5 00 c6 8f e2 08 ca 8c e2 e0 f3 bc e5 00 c6 8f    ................

322d843f: e2 08 ca 8c e2 d8 f3 bc e5 00 c6 8f e2 08 ca 8c    ................

322d844f: e2 d0 f3 bc e5 00 b0 a0 e3 00 e0 a0 e3 04 10 9d    ................

322d845f: e4 0d 20 a0 e1 04 20 2d e5 04 00 2d e5 10 c0 9f    .. ... -...-....

322d846f: e5 04 c0 2d e5 0c 00 9f e5 0c 30 9f e5 dc ff ff    ...-......0.....

322d847f: eb ed ff ff eb 00 86 00 00 0c 85 00 00 04 86 00    ................

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322d958f: 00 00 40 00 00 9c 00 00 00 00 00 00 00 00 00 00    ..@.............

322d959f: 00 04 00 00 00 04 00 00 00 da 00 00 00 01 00 00    ................

322d95af: 00 03 00 00 00 9c c0 00 00 9c 40 00 00 04 00 00    ..........@.....

322d95bf: 00 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00    ................

322d95cf: 00 e0 00 00 00 08 00 00 00 03 00 00 00 a0 c0 00    ................

322d95df: 00 a0 40 00 00 04 00 00 00 00 00 00 00 00 00 00    ..@.............

322d95ef: 00 01 00 00 00 00 00 00 00 e5 00 00 00 03 00 00    ................

322d95ff: 70 00 00 00 00 00 00 00 00 a0 40 00 00 2c 00 00    p.........@..,..

322d960f: 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00    ................

322d961f: 00 f5 00 00 00 01 00 00 00 00 00 00 00 00 00 00    ................

322d962f: 00 cc 40 00 00 18 00 00 00 00 00 00 00 00 00 00    ..@.............

322d963f: 00 01 00 00 00 00 00 00 00 01 00 00 00 03 00 00    ................

MINI2440 # 

"People think that computer science is the art of geniuses but the actual reality is the opposite, just many people doing things that build on each other, like a wall of mini stones."
- Donald Knuth